This invention relates to computer systems which are suitable for process sequence controllers and, more particularly, to a computer system in which a microcomputer repeatedly processes single bits of data.
The basic operation of a computer system including a microcomputer for a process controller is described below. After reading an external process signal (which is referred to hereinafter as "input data"), the microcomputer processes the input data according to a program and the processed data becomes an output of a control signal or an alarm signal indicating an abnormal condition.
The computer system comprises an input interface which reads external data as input data, an output interface which produces a control or alarm signal as an output signal, a microcomputer (which is referred to hereinafter as a "CPU") in which input data are processed according to a program, and a memory in which the input data from the input interface, the output data from the output interface and the program are stored. Moreover, the elements related to the computer system are a data bus connecting the aforementioned elements and an address bus which transfers an address signal from the CPU to the memory.
The data which are used most often in the industrial computer system are values of temperature, pressure, voltage, current, resistance, ON and OFF switch positions and open and closed valve positions. For all but the latter two data, one byte of eight bits or one word of sixteen words is processed as a minimum data unit. The CPU can process the bytes or words in parallel. When the data signals from the memory or the input/output interface are accessed, the eight bit data are read into the CPU or are read out from the CPU.
One bit of data in industrial computer systems, however, is expressed as either the state of a switch or the position of a valve. Processing one bit of data is especially disadvantageous in a sequence controller (a programmable logic controller).
The operation of an industrial computer system acting as a sequence controller will be described with reference to FIGS. 1 to 3.
Referring to FIG. 1, a CPU 101, containing eight bit accumulator 102, addresses the input interface 105, reads input data from that interface and processes the data. An address bus line 103 transfers an address signal from the CPU 101. A data bus line 104 transfers eight bit data between the elements of the computer system.
The input data are obtained from external processes S0 to S7 of, for example, switches or relay contacts. An input interface 105 transfers the input data from a gate circuit 106 addressed by the CPU 101 to the data bus line 104. Accordingly, the input interface 105 can decode an address (not shown in FIG. 1).
An output interface 107 latches the processed control signal or the alarm signal from CPU 101 in a latch circuit 108 when the output interface 107 receives the address signal from the CPU 101. An actuator 109 is controlled by a data bit latched in the output interface 107. A memory 110 stores input data, output data and the program. The memory 110 has an eight bit arrangement as shown in FIG. 2.
After reading the input data, the CPU processes the data according to a control program (not shown) to derive processed output data. The data processing system is very busy processing the one bit.
To explain the disadvantages of the prior art system, the programming steps of a simple sequence operation is described below. In the operation, a valve 109 is controlled when the relay contact S4 and the switch S5 are closed. The input data from S4 and S5 are stored in bits No. 4 and 5 of the address word No. 0 in memory 110. The output data for valve 109 is stored in the bit No. 2 of the address No. 1.
For the process to be performed, CPU 101 stores the input data from S4 into the accumulator 102 through the input interface 105 and then stores that data into bit No. 4 of the address No. 0.
Similarly, the CPU 101 stores the input data from S5 into the accumulator 102 and stores the data into bit No. 5 of the word at memory address No. 0.
The CPU 101 determines the logical AND of the data in bits 4 and 5 of word 0 and stores the result in bit No. 2 of the word at memory address No. 1. Only bit No. 2 of the address No. 1 is changed; the other bits of the word in address No. 1 are not changed.
The program steps to accomplish this procedure will be described with reference to FIG. 3 which shows the contents of accumulator 102. It is assumed that the data from S4 and S5 have already been read into word 0 of memory.
CPU 101 addresses word 0 in memory 110 and stores the eight bits of data from that word into accumulator 102 (FIG. 3(a)). The CPU 101 shifts the data in bit number 4 in accumulator 102 to the bit number 0 position by shifting the accumulator four bits to the right (FIG. 3(b)).
The contents C1 of accumulator 102 are temporarily stored in another accumulator or at another address of memory 110 (FIG. 3(c)). C2 represents the contents of the other accumulator or memory location.
CPU 101 addresses memory at address "0" of memory 101 and stores the eight bits of data from memory into accumulator 102 (FIG. 3(d)). CPU 101 then shifts the data in accumulator 101 five bits to the right so that bit 0 contains the contents of bit 5 of memory word 0 (FIG. 3(e)).
The CPU 101 "ANDs" the contents of the other accumulator or memory location C2, and the accumulator 102 producing the AND of the data from S4 and S5 in the bit No. 0 of the accumulator 102 (FIG. 3(f)).
The fixed data word g1, having bit No. 0 as "1" and the other bits as "0", is fetched from the memory 110. The CPU 101 performs a logical AND between the fixed data word g1 and the contents of the accumulator 102 so the accumulator 102 has a "0" in bit locations 1 to 7 (FIG. 3(g)).
The CPU 101 shifts the data in bit location 0 in the accumulator 102, which is (bit No. 5).multidot.(bit No. 4), to bit position 2 by shifting the accumulator two bits to the left (FIG. 3(h)). This word is stored in memory or in another accumulator (3 (i)).
The CPU 101 next addresses word 1 of the memory 110 and stores the eight bits of that word into the accumulator 102 (FIG. 3(j)). The fixed data k1 in which bit location 2 is "0" and the other bits are "1" is fetched from the memory 110 and the CPU 101 performs a logical AND between the fixed data k1 and the contents of the accumulator 102. At this point, bit location 2 of the accumulator 102 contains a "0" and the other data bits in the accumulator 102 remain the same (FIG. 3(k)).
The CPU 101 then ORs the contents of the accumulator 102 and the contents of the other accumulator or memory location containing the logical AND of bit Nos. 4 and 5 (FIG. 3(l). This places the logical AND of those bits in bit position 2. The CPU 101 stores the resulting word into the memory 110 at word 1.
Later, the CPU 101 fetches the data from word 1 into the accumulator 102 and addresses the output interface 107. CPU 101 latches the data into the latch circuit 108 of the output interface 107 to control the valve 109.
As can be seen, bit operations in this type of microcomputer requires many steps for a simple logical operation. Normally, the general sequence controller has many output and input data. The CPU must not only perform logical OR operations but also logical AND, NAND and NOR operations. Accordingly, the CPU 101 operation is very complicated.
If the program technique in the computer system has a subroutine for the AND and OR operation, the speed of the computer slows significantly.